In fabricating microelectronic semiconductor devices and the like on a semiconductor wafer (substrate or chip), e.g., of silicon, to form an integrated circuit (IC), etc., various metal layers and insulation layers are deposited in selective sequence, and in some cases oxide layers are grown in situ on the wafer. To maximize integration of device components in the available wafer area to fit more components in the same area, increased IC miniaturization is utilized. Reduced pitch dimensions are needed for denser packing of components per present day very large scale integration (VLSI), e.g., at sub-micron (below 1 micron, i.e., 1,000 nanometer or 10,000 angstrom) dimensions.
A typical conventional technique for forming a patterned conductive multilayer, e.g., dual damascene (i.e., inlaid), arrangement on a semiconductor wafer, e.g., of silicon, involves the deposition thereon of successive levels of alternating insulation layers, e.g., of silicon dioxide, and metal layers, e.g., of aluminum, copper or tungsten, with appropriate photolithographic patterning and then etching, to provide successive level conductive metal lines in the associated insulation layers.
As to the steps for providing the lowest or first level conductive metal line arrangement, (1) a first level insulation layer is deposited on the semiconductor wafer and subjected to photolithographic patterning and then etching to form an arrangement of first level trenches therein; (2) a first level metal layer is deposited on the first level insulation layer to fill the first level trenches; and (3) the first level metal layer is subjected to metal chemical mechanical polishing (CMP) to form an arrangement of first level metal lines in the first level trenches between intervening insulation layer portions while removing the remainder of the first level metal layer to prevent touching and thus short circuiting between adjacent first level metal lines.
As to the steps for providing the next higher or second level conductive metal line arrangement, (4) a second level insulation layer is deposited on the first level insulation layer to cover the first level arrangement of metal lines; (5) the second level insulation layer is subjected to photolithographic patterning and then etching to form an arrangement of second level trenches therein; (6) a second level metal layer is deposited on the second level insulation layer to fill the second level trenches; and (7) the second level metal layer is subjected to metal CMP to form an arrangement of second level metal lines in the second level trenches between intervening insulation layer portions while removing the remainder of the second level metal layer to prevent touching and short circuiting between adjacent second level metal lines.
As to the providing of the next higher or third level, e.g., triple damascene, conductive metal line arrangement, if any, the above steps (4) to (7) are repeated to form such further level conductive metal line arrangement. The arrangements of metal lines in the multilayer arrangement are interconnected by metallization through vias or small holes or apertures (windows) etched in the intervening insulation layers in known manner. The semiconductor wafer is then further processed to provide the final wafer product.
One problem is that metal CMP introduces topography into the semiconductor wafer due to dishing and erosion of metal line regions. This topography is transferred conformally to higher levels of the multilayer arrangement, leading to smaller process windows for subsequent pressing and in general also to larger yield losses for the final wafer product.
Higher pattern factor metal lines erode more than lower pattern factor metal lines during metal CMP since a given area higher pattern factor metal line region contains more metal and less trench-forming intervening insulation layer material than a like area lower pattern factor metal line region. The metal is readily selectively removed by the metal CMP, e.g., using an aqueous colloidal alumina abrasive slurry in conventional manner. On the other hand, as the slurry is designed to remove metal and not insulation layer material, the latter is not significantly removed yet is eroded to a minor extent by the metal CMP.
Moreover, during metal CMP of a lower level metal layer, variations in pattern factors in the arrangement of metal lines lead to non-uniform dishing of the metal lines and erosion of the surrounding or intervening areas of the insulation layer. This also introduces topography into the semiconductor wafer.
It is desirable to have a process which offsets such non-uniform dishing of the lower level metal lines and erosion of surrounding or intervening insulation layer areas, which reduces such topography, which is low in cost, and in particular which reduces topography height differences between intervening insulation layer areas and metal lines, and which also reduces topography differences between metal lines with different pattern factors in the same lower level metal line arrangement. This would provide a more planar (flatter) layer arrangement permitting wider (larger) process windows and higher yield processing at subsequent (higher) levels of the multilayer arrangement.